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asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 1 - general description the ak 5384 is a 4 - channel a/d converter with wide sampling rate of 8khz ~ 96khz and is suitable for multi - channel audio system. the ak5384 achieves high accuracy and low cost by using enhanced dual bit d s tech niques. the ak5384 supports master mode and tdm format. therefore, the ak5384 is suitable for multi - channel audio system . f eatures o 4 - channel d s adc o differential inputs o digital hpf for dc - offset cancel o s/(n+d): 100db@5v for 48khz o dr: 107db@5v for 48khz o s/n: 107db@5v for 48khz o sampling rate ranging from 8khz to 96khz o master clock: 256fs/384fs/512fs/768fs ( ~ 48khz) 256fs/384fs ( ~ 96khz) o ttl digital input level o output format: 24bit msb justified, i 2 s or tdm o cascade tdm interface o master & slave mode o overflow flag o power supply: 4.75 to 5.25v o power supply for output buffer: 3.0 to 5.25v o ta = - 40 ~ 85 c o 28pin vsop d s modulator lin1- lrck bick sdto1 vcom clock divider a vss avdd decimation filter audio interface voltage reference d vss dvdd pdn lin1+ d s modulator rin1- decimation filter rin1+ d s modulator lin2- decimation filter lin2+ d s modulator rin2- decimation filter rin2+ sdto2 dif tdm0 m/s mclk cks tdmin tdm1 tvdd ovf 107db 24 - bit 96khz 4 - channel adc ak5384
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 2 - n ordering guide AK5384VF - 40 ~ +85 c 28pin vsop (0.65mm pitch) akd5384 evaluation board for ak5384 n pin layout rin2+ rin2- avss avdd lin2+ lin2- test vcom tdm1 tdm0 tdmin mclk ovf dif top view 8 7 6 5 4 3 2 1 21 22 23 24 25 26 27 28 rin1+ rin1- pdn cks m/s lin1- lin1+ 9 10 11 12 13 14 18 19 20 tvdd 15 16 17 lrck bick sdto2 dvdd dvss sdto1
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 3 - p in /f unction no. pin name i/o function 1 lin2+ i adc2 lch positive analog input pin 2 lin2 - i adc2 lch negative analog input pin 3 rin2+ i adc2 rch posit ive analog input pin 4 rin2 - i adc2 rch negative analog input pin 5 test i test pin (connected to avss) 6 vcom o common voltage output pin, avdd/2 normally connected to avss with a 0.1 m f ceramic capacitor in parallel with an electrolytic c apacitor less than 2.2 m f. 7 avss - analog ground pin 8 avdd - analog power supply pin, 4.75 ~ 5.25v 9 dif i audio interface format pin ? l ? : 24bit msb justified, ? h ? : 24bit i 2 s compatible 10 tdm1 i tdm i/f bick frequency select pin ? l ? : 25 6fs, ? h ? : 128fs 11 tdm0 i tdm i/f format enable pin ? l ? : normal mode, ? h ? : tdm mode 12 tdmin i tdm data input pin 13 mclk i master clock input pin 14 ovf o analog input overflow detect pin this pin goes to ? h ? if one of four analog inp uts overflows. 15 lrck i/o output channel clock pin ? l ? output in master mode at power - down mode. 16 bick i/o audio serial data clock pin ? l ? output in master mode at power - down mode. 17 sdto2 o adc2 audio serial data output pin ? l ? output a t power - down mode. 18 sdto1 o adc1 audio serial data output pin ? l ? output at power - down mode. 19 tvdd - output buffer power supply pin, 3.0 ~ 5.25v 20 dvdd - digital power supply pin, 4.75 ~ 5.25v 21 dvss - digital ground pin 22 pdn i power - down mode pin when ? l ? , the circuit is in power - down mode. the ak5384 should always be reset upon power - up. 23 cks i master clock select pin ? l ? : 256fs, ? h ? : 512fs this pin is enabled in master mode. 24 m/s i master / slave mode pin ? l ? : slave mode, ? h ? : master mode 25 rin1 - i adc1 rch negative analog input pin 26 rin1+ i adc1 rch positive analog input pin 27 lin1 - i adc1 lch negative analog input pin 28 lin1+ i adc1 lch positive analog input pin note: all digital input pins should not be left floating.
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 4 - a bsolute maximum ratings (avss , dvss= 0v ; note 1) parameter symbol min max units power supplies: analog digital output buffer |avss ? dvss| (note 2) avdd dvdd tvdd d gnd - 0.3 - 0.3 - 0.3 - 6.0 6.0 6.0 0.3 v v v v input current, any pin except supplies iin - 10 ma analog input voltage vina - 0.3 avdd+0.3 v digital input voltage (except bick, lrck pins) (bick, lrck pins) vind1 vind2 - 0.3 - 0.3 dvdd+0.3 tvdd+0.3 v v ambient temperature (powered applied) ta - 40 85 c storage temperature tstg - 65 150 c note 1. all voltages with respect to ground. note 2. avss and dvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the de vice. normal operation is not guaranteed at these extremes. recommended operating conditions ( avss, dvss=0v ; note 1) parameter symbol min typ max units power supplies (note 3) analog digital output buffer avdd dvdd tvdd 4.75 4.75 3.0 5.0 5.0 5.0 5.25 5.25 5.25 v v v note 1 . all voltages with respect to ground. note 3. the power up sequence between avdd, dvdd and tvdd is not critical. warning : akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 5 - anal og characteristics ( ta=25 c ; avdd=dvdd=tvdd=5.0v ; a vss=dvss=0v; fs=4 8k hz , 96khz; i/f format=mode 0; signal frequency =1khz ; measurement frequency=20hz ~ 20khz at fs=48khz, 40hz ~ 40khz at fs=96khz; unless otherwise specified) parameter min typ max units adc analog input characteristics: resolution 24 bits s/(n+d) ( - 1dbfs ) fs=48khz fs=96khz 88 82 100 94 db db dr ( - 60dbfs ) fs=48khz, a - weighted fs=96khz 100 94 107 102 db db s/n fs=48khz, a - weighted fs=96khz 100 9 4 107 102 db db interchannel isolation 90 110 db dc accuracy: interchannel gain mismatch 0.1 0.5 db gain drift 100 150 ppm/ c input voltage (note 4) 2.7 2.9 3.1 vpp input resistance 18 11 26 16 k w k w power supply rejection ( note 5 ) 50 - db power supplies power supply current (avdd+dvdd+tvdd) normal operation ( pdn pin = ? h ? , fs=48khz ) (note 6) normal operation (pdn p in = ? h ? , fs=96khz) (note 6) power - down mode ( pdn pin = ? l ? ) ( note 7 ) 43 55 10 65 83 100 ma ma m a note 4. this value is the full scale (0db) of the input voltage. this voltage is input to lin(rin)+ and lin(rin) - pin, and is proportional to avdd. (vin = 0.58 avdd) note 5. psr is applied to avdd, dvdd and tvdd with 1khz, 50mvpp. note 6. avdd=28ma; dvdd=15ma@48khz&5v, dvdd=26ma@96khz&5v(typ). note 7. all digital input pins are fixed to dvdd or dvss.
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 6 - fi lter characteristics (fs=48khz) ( ta= 25 c ; a vdd, dvdd = 4.75 ~ 5.25v; tvdd = 3.0 ~ 5.25 v ; fs=4 8k hz ) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 8) - 0.005db - 0.02db - 0.06db - 6.0db pb 0 - - - 21.768 22.0 24.0 21.5 - - - khz khz khz khz stopband (note 8) sb 26.5 khz passband ripple pr 0.005 db stopband attenuation sa 80 db group delay ( note 9 ) gd 27.6 1/f s group delay distortion d gd 0 m s adc digital filter (hpf) : frequency response ( note 8 ) - 3db - 0.5db - 0.1db fr 1.0 2.9 6.5 hz hz hz filter characteristics (fs=96khz) ( ta= 25 c ; a vdd, dvdd = 4.75 ~ 5.25v; tvdd = 3.0 ~ 5.25 v ; fs=96 k hz ) parame ter symbol min typ max units adc digital filter (decimation lpf): passband ( note 8) - 0.005db - 0.02db - 0.06db - 6.0db pb 0 - - - 43.536 44.0 48.0 43.0 - - - khz khz khz khz stopband (note 8) sb 53.0 khz passband ripple pr 0.005 db stopband attenuation sa 80 db group delay ( note 9 ) gd 27.6 1/fs group delay distortion d gd 0 m s adc digital filter (hpf) : frequency response ( note 8 ) - 3db - 0.5db - 0.1db fr 2.0 5.8 13.0 hz hz hz note 8. the passband and stopband frequencies scale with fs. note 9. the calculated delay time induced by digital filtering. this time is from the input of an analog signal to the setting of 24 bit data both channels to the adc output register for adc. dc characteristics ( ta= 25 c ; avdd, dvdd=4.75 ~ 5.25 v ; tvdd=3.0 ~ 5.25v) parameter symbol min typ m ax units high - level input voltage (tvdd= 3.0 ~ 3.6v ) low - level input voltage (tvdd= 3.0 ~ 3.6v ) h igh - level input voltage (tvdd= 3.6 ~ 5.25v ) low - level input voltage (tvdd= 3.6 ~ 5.25v ) vih vil vih vil 2.2 - 2.7 - - - - - - 0.8 - 0.5 v v v v high - level output voltage (iout= - 100 m a ) low - level output voltage (iout=100 m a) voh vol tvdd - 0.5 - - - - 0.5 v v input leakage current iin - - 10 m a
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 7 - switching characteristics ( ta= 25 c ; avdd, dvdd = 4.75 ~ 5.25 v ; tvdd=3.0 ~ 5.25v ; c l =2 0pf ) parameter symbol min t yp max units master clock timing master clock 256fs: pulse width low pulse width high 384fs: pulse width low pulse width high 512fs: pulse width low pulse width high 768fs: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 2.048 16 16 3.072 11 11 4.096 16 16 6.144 11 11 12.288 18.432 24.576 36.864 24.576 36.864 24.576 36.864 mhz ns ns mhz ns ns mhz ns ns mhz ns ns lrck timing (slave mode) normal mode (tdm1= ? l ? , tdm0= ? l ? ) lrck frequency duty cycle fs duty 8 45 96 55 khz % tdm256 mode (tdm1= ? l ? , tdm0= ? h ? ) lrck frequency ? h ? time ? l ? time fs tlrh tl rl 8 1/256fs 1/256fs 48 khz ns ns tdm128 mode (tdm1= ? h ? , tdm0= ? h ? ) lrck frequency ? h ? time ? l ? time fs tlrh tlrl 8 1/128fs 1/128fs 96 khz ns ns lrck timing (master mode) normal mode (tdm1= ? l ? , tdm0= ? l ? ) lrck fre quency duty cycle fs duty 8 50 96 khz % tdm256 mode (tdm1= ? l ? , tdm0= ? h ? ) lrck frequency ? h ? time (note 10) fs tlrh 8 1/8fs 48 khz ns tdm128 mode (tdm1= ? h ? , tdm0= ? h ? ) lrck frequency ? h ? time (note 10) fs tlrh 8 1/4fs 96 khz ns note 10 . ? l ? time at i 2 s format.
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 8 - parameter symbol min typ max units audio interface timing (slave mode) normal mode (tdm1= ? l ? , tdm0= ? l ? ) bick perio d bick pulse width low pulse width high lrck edge to bick ? - ? (note 11) bick ? - ? to lrck edge (note 11) lrck to sdto1/2 ( msb ) ( except i 2 s mode ) bick ? ? to sdto1/2 tbck tbckl tbckh tlrb tblr tlrs tbsd 160 65 65 3 0 30 35 35 ns ns ns ns ns ns ns tdm256 mode (tdm1= ? l ? , tdm0= ? h ? ) bick period bick pulse width low pulse width high lrck edge to bick ? - ? (note 11) bick ? - ? to lrck edge (note 11) bick ? ? to sdto1 /2 tbck tbckl tbckh tlrb tblr tbsd 81 32 32 20 20 20 ns ns ns ns ns ns tdm128 mode (tdm1= ? h ? , tdm0= ? h ? ) bick period bick pulse width low pulse width high lrck edge to bick ? - ? (note 11) bick ? - ? to lrck edge (note 11) bick ? ? to sdto1 (note 12) tbck tbckl tbckh tlrb tblr tbsd 81 32 32 20 20 20 ns ns ns ns ns ns audio interface timing (master mode) normal mode (tdm1= ? l ? , tdm0= ? l ? ) bick frequency bick d uty bick ? ? to lrck bick ? ? to sdto1/2 fbck dbck tmblr tbsd - 20 - 40 64fs 50 20 40 hz % ns ns tdm256 mode (tdm1= ? l ? , tdm0= ? h ? ) bick frequency bick duty (note 13) bick ? ? to lrck bick ? ? to sdto1/2 fbck dbck tmblr tbsd - 12 - 20 256fs 50 12 20 hz % ns ns tdm128 mode (tdm1= ? h ? , tdm0= ? h ? ) bick frequency bick duty bick ? ? to lrck bick ? ? to sdto1 (note 12) fbck dbck tmblr tbsd - 12 - 20 128fs 50 12 20 hz % ns ns p ower - down & reset timing pdn pulse width (note 14) pdn ? - ? to sdto1/2 valid (note 15) tpd tpdv 150 516 ns 1/fs note 11. bick rising edge must not occur at the same time as lrck edge. note 1 2. sdto2 output is fixed to ? l ? . note 13. this value is mclk=512fs. duty cycle is not guaranteed when mclk=256fs/384fs. note 14. the ak5384 can be reset by bringing the p dn pin = ? l ? . note 15. this cycle is the number of lrck rising edges from the pdn pin = ? h ? .
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 9 - n timing diagram 1/fclk tclkl vih tclkh mclk vil 1/fs lrck vih vil tbck tbckl vih tbckh bick vil clock timing (tdm0 pin = ? l ? ) 1/fclk tclkl vih tclkh mclk vil 1/fs lrck vih vil tlrl tlrh tbck tbckl vih tbckh bick vil clock timing (tdm0 pin = ? h ? )
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 10 - lrck vih vil tblr bick vih vil tlrs sdto 50%tvdd tlrb tbsd audio interface timing (slave mode, tdm0 pin = ? l ? ) lrck vih vil tblr bick vih vil sdto 50%tvdd tlrb tbsd audio interface timing (slave mode, tdm0 pin = ? h ? ) note: sdto shows sdto1 and sdto2.
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 11 - lrck bick 50%tvdd sdto 50%tvdd tbsd tmblr dbck 50%tvdd audio interfa ce timing (master mode) tpd pdn vil pdn vih vil tpdv sdto 50%tvdd power down & reset timing note: sdto shows sdto1 and sdto2.
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 12 - operation overview n system clock the external clocks which are required to operate the ak5384 are mclk(256fs/384fs/512fs/768fs), b ick (48fs ~ ), lrck(1fs) in slave mode (m/s pin = ? l ? ). mclk should be synchronized with lr ck but the phase is not critical . when 384fs, 512fs or 768fs clock is input to mclk pin, the internal master clock becomes 256fs(=384fs x 2/3=512fs x 1/2=768fs x 1/3) a utomatically. table 1 illustrates standard audio word rates and corresponding frequencies used in the ak5384. in master mode (m/s pin = ? h ? ), mclk select 256fs or 512fs by cks pin. but 384fs and 768fs are not supported. 512fs does not support 96khz sampli ng. all external clocks (mclk, bick, lrck) should always be present whenever the ak5384 is in normal operation mode ( pdn pin = ? h ? ). if these clocks are not provided, the ak5384 may draw excess current and may fall into unpredictable operation. this is be cause the device utilizes dynamic refreshed logic internally. if the external clocks are not present, the ak5384 should be in the power - down mode ( pdn pin = ? l ? ). after exiting reset at power - up etc., the ak5384 is in the power - down mode until mclk and lrc k are input. in master mode, the master clock (mclk) must be provided unless pdn pin = ? l ? . mclk bick fs 256fs 384fs 512fs 768fs 64fs 128fs 32.0khz 8.1920mhz 12.2880mhz 16.3840mhz 24.576mhz 2.0480mhz 4.0960mhz 44.1khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 2.8224mhz 5.6448mhz 48.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz 3.0720mhz 6.1440mhz 96.0khz 24.5760mhz 36.8640mhz n/a n/a 6.1440mhz n/a table 1. system clock example (slave mode) mclk cks 8khz fs 48khz 48khz < fs 96khz l 256 fs 256fs h 512fs n/a table 2. master clock frequency select (master mode) n audio interface format 12 types of audio data interface can be selected by t he tdm1 - 0, m/s and dif pins as shown in table 3. the audio data format can be selected by the dif p in. in all format s the serial data is msb-first, 2's compliment format. the sdto 1/2 is clocked out on the falling edge of bick . in normal mode, mode 0 - 1 are the s lave m ode , and bick is available up to 128fs at fs=48khz. bick outputs 64fs clock in mode 2 - 3 . in tdm256 mode, the serial data of all adc (four channels) is output from the sdto1/2 pins. bick should be fixed to 256fs. in the slave mode, ? h ? time and ? l ? time of lrck should be 1/256fs at least. in the master mode, ? h ? time ( ? l ? time at i 2 s mode) o f lrck is 1/8fs typically. tdm256 mode does not support 96khz sampling. in tdm128 mode, the serial data of all adc (four channels) is output from the sdto1 pin. the sdto2 output is fixed to ? l ? . bick should be fixed to 128fs. in the slave mode, ? h ? time a nd ? l ? time of lrck should be 1/128fs at least. in the master mode, ? h ? time ( ? l ? time at i 2 s mode) of lrck is 1/4fs typically. tdm128 mode supports up to 96khz sampling.
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 13 - lrck bick mode tdm1 tdm0 m/s dif sdto i/o i/o 0 l 24bit, m sb justified h/l i 48 - 128fs i 1 l h 24bit, i 2 s compatible l/h i 48 - 128fs i 2 l 24bit, msb justified h/l o 64fs o 3 normal l l h h 24bit, i 2 s compatible l/h o 64fs o 4 l 24bit, msb justified - i 256fs i 5 l h 24bit, i 2 s compatible i 256f s i 6 l 24bit, msb justified - o 256fs o 7 tdm256 l h h h 24bit, i 2 s compatible o 256fs o 8 l 24bit, msb justified - i 128fs i 9 l h 24bit, i 2 s compatible i 128fs i 10 l 24bit, msb justified - o 128fs o 11 tdm128 h h h h 24bit, i 2 s compati ble o 128fs o 12 n/a h l n/a n/a n/a n/a n/a n/a n/a table 3. audio interface formats lrck bick(64fs) sdto1/2(o) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 lch data rch data 12 11 10 23:msb, 0:lsb figure 1. mode 0, 2 timing (normal mode, msb justified) lrck bick(64fs) sdto1/2(o) 0 1 2 3 23 24 25 26 0 0 1 31 29 30 23 22 1 23:msb, 0:lsb lch data rch data 2 0 2 3 23 24 25 26 0 31 29 30 23 22 1 2 0 1 figure 2. mode 1, 3 timing (normal mode, i 2 s compa tible) 23 lrck (mode 4) bick (256fs) sdto1 22 0 l1 32 bick 256 bick 22 0 r1 32 bick 22 23 23 22 0 l2 32 bick 22 0 r2 32 bick 23 23 lrck (mode 6) figure 3. mode 4, 6 timing (tdm256 mode, msb justified)
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 14 - lrck (mode5) bick (256fs) sdto1 23 0 l1 32 bick 256 bick 23 0 r1 32 bick 23 23 0 l2 32 bick 23 0 r2 32 bick lrck (mode 7) figure 4. mode 5, 7 timing (tdm256 mode, i 2 s compatible) lrck (mode 8) bick (128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick sdto1 22 0 22 0 22 0 22 0 23 23 23 23 22 23 lrck (mode 10) figure 5. mode 8, 10 timing (tdm128 mode, m sb justified) lrck (mode 9) bick (128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick sdto1 22 0 22 0 22 0 22 0 23 23 23 23 23 lrck (mode 11) figure 6. mode 9, 11 timing (tdm128 mode, i 2 s compatible) n master mode and slave mode the m/s pin selects either master or slave mode. m/s pin = ? h ? selects master mode and ? l ? selects slave mode. the ak5384 outputs bick and lrck in master mode. in slave mode, mclk, bick and lrck are input externally. m/s pin mode bick, lrck l slave mode bick = input lrck = input h master mode bick = output lrck = output table 4. master mode/slave mode
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 15 - n digital high pa ss filter the adc has a digital high pass filter for dc offset cancellation. the cut - off frequency of the hpf is 1.0hz(@fs=48khz) and scales with sampling rate (fs). n overflow detection the ak5384 has overflow detect function for analog input. ovf pin goes to ? h ? if one of 4 - channels overflows (more than - 0. 3dbfs). ovf output for overflowed analog input has the same group delay as adc (gd=27.6/fs=575 s@fs=48khz). ovf is ? l ? for 516/fs (=10.75ms@fs=48khz) after pdn pin = ? - ? , and then overflow detection is enabled. n power down the ak5384 is placed in the power - down mode by bringing pdn pin ? l ? and the digital filter is also reset at the same time. this reset should always be done after power - up. in the power - down mode, the vcom are avss level. an ana log initialization cycle starts after exiting the power - down mode. therefore, the output data sdto1/2 becomes available after 516 cycles of lrck clock. during initialization, the adc digital data outputs of both channels are forced to a 2 ? s complement ? 0 ? . the adc outputs settle in the data corresponding to the input signals after the end of initialization (settling approximately takes the group delay time). normal operation internal state pdn power-down initialize normal oper ation 516/fs(10.75ms@fs=48khz) idle noise gd gd ? 0 ? data a/d in (analog) a/d out (digital) clock in mclk,lrck,bick (1) (2) (3) ? 0 ? data idle noise notes: (1) digital output corresponding to analog input has the gr oup delay (gd). (2) adc output is ? 0 ? data at the power - down state. (3) when the external clocks (mclk, bick, lrck) are stopped, the ak5384 should be in the power - down state. figure 7. power - down/up sequence example n system reset the ak5384 sho uld be reset once by bringing pdn pin ? l ? after power - up. the internal timing starts clocking by the rising edge (falling edge at i 2 s mode) of lrck upon exiting from reset.
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 16 - n cascade tdm mode the ak5384 supports cascading of up to two devices in a dais y chain configuration at tdm256 mode. in this mode, sdto2 pin of device #1 is connected to tdmin pin of device #2. sdto1 pin of device #2 can output 8ch tdm data multiplexed with 4ch tdm data of device #1 and 4ch tdm data of device #2. figure 8 shows a co nnection example of a daisy chain. 48khz 256fs 8ch tdm lrck ak5384 #1 bick tdmin sdto1 sdto2 mclk 256fs or 512fs gnd lrck ak5384 #2 bick tdmin sdto1 sdto2 mclk figure 8 . cascade tdm connection diagram lrck bick(256fs) #1 sdto1(o) 22 0 l1 32 bick 256 bick 22 0 r1 32 bick 22 23 23 23 22 0 l2 32 bick 22 0 r2 32 bick 23 23 #1 sdto2(o) 22 0 l1 32 bick 22 0 r1 32 bick 23 23 22 0 l2 32 bick 22 0 r2 32 bick 23 23 #2 tdmin( i) 22 0 l1 32 bick 22 0 r1 32 bick 23 23 22 0 l2 32 bick 22 0 r2 32 bick 23 23 #2 sdto1(o) 22 0 l1 32 bick 22 0 r1 32 bick 22 23 23 23 22 0 l2 32 bick 22 0 r2 32 bick 23 23 22 0 l1-#1 32 bick 22 0 r1-#1 32 bick 23 23 22 0 l2-#1 32 bick 22 0 r2-#1 32 bick 23 23 figure 9 . cascade tdm timing
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 17 - system design figure 10 shows the system connection diagram. an evaluation board is ava ilable which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. 0.1 m 10 m lin2+ 1 2 3 4 5 6 7 8 9 10 11 lin2- rin2+ rin2- test vcom avss avdd dif tdm1 tdm0 ak5384 dsp and up 28 27 26 lin1+ lin1- rin1+ analog supply 4.75 ~ 5.25v 12 tdmin 13 mclk 14 ovf reset 25 24 rin1- m/s 23 22 cks pdn dvss dvdd 19 18 tvdd sdto1 17 16 sdto2 bick 15 lrck 0.1 m 10 m digital supply 4.75 ~ 5.25v 20 21 0.1 m digital supply 3.0 ~ 5.25v 0.1 m 2.2 m note: - avss and dvss of the ak5384 should be distributed separately from the ground of external digit al devices (mpu, dsp etc.). - all digital input pins should not be left floating. figure 10. typical connection diagram (normal mode)
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 18 - 1. grounding and power supply decoupling the ak5384 requires careful attention to power supply and grounding arran gements. avdd and dvdd are usually supplied from the analog supply in the system. alternatively if avdd and dvdd are supplied separately, the power up sequence is not critical. avss and dvss of the ak5384 must be connected to analog ground plane. system an alog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak5384 as possible, with the small value ceramic capacitor being the closest. 2. voltage reference inputs the differential voltage between avdd and avss sets the analog input range. vcom is a signal ground of this chip. an electrolytic capacitor 2.2 m f parallel with a 0.1 m f ceramic capacitor attached to vcom pin eliminates the effe cts of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the ak5384. 3. analog inputs the ak5384 accepts +5v supply voltage . any voltage which exceeds the upper limit of avdd+0.3v and lower limit of avss - 0.3v and any current beyond 10ma for the analog input pins (lin+/ - , rin+/ - ) should be avoided. excessive currents to the input pins may damage the device. hence input pins mus t be protected from signals at or beyond these limits. use caution specially in case of using 15v in other analog circuits. the analog inputs are differential and internally biased to the common voltage (avdd/2) with 26k w (typ). the input signal range bet ween lin(rin)+ and lin(rin) - scales with the supply voltage and nominally 0.58 x avdd. the ak5384 can accept input voltages from avss to avdd. the adc output data format 2 ? s compliment. the internal hpf removes the dc offset. the ak5384 samples the analo g inputs at 64fs. the digital filter rejects noise above the stop band except for multiples of 64fs.
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 19 - 4. external analog inputs circuit figure 11 shows an input buffer circuit example 1. the input level of this circuit is 5.7vpp (ak5384: typ. 2.9vpp). 5.7vpp analog in 22 m 10k w 5.1k w vp+ vp- njm5532 vp+ = +15v vp- = -15v 4.7k w 4.7k w njm5532 bias bias 10 m 0.1 m bias 10k 10k va va = +5v 330 w ain+ ak5384 2.9vpp 1.5n 330 w 2.9vpp ain- figure 11. input buffer circuit example 1 (dc coupled single - end input) figure 12 shows an input buffer circuit example 2. the input level of this circuit is 5.7vpp (ak5384: typ. 2.9vpp). 5.7vpp analog in 22 m 10k w 5.1k w vp+ vp- njm5532 vp+ = +15v vp- = -15v 4.7k w 4.7k w njm5532 10 m 330 w ain+ ak5384 2.9vpp 1.5n 10 m 330 w 2.9vpp ain- figur e 12. input buffer circuit example 2 (ac coupled single - end input) figure 13 shows an input buffer circuit example 3. the input level of this circuit is 2.9vpp (ak5384: typ. 2.9vpp). analog in analog in 330 w 330 w 1.5n 2.9vpp 2.9vpp 10 m 10 m ain+ ain- ak5384 figure 13. input buffer circuit example 3 (differential input)
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 20 - package 0.1 0.1 0 -10 detail a seating plane note: dimension "*" does not include mold flash. | 0.10 0.1 5- 0. 0 5 0. 22 0.1 0.65 *9.8 0.2 1.25 0.2 a 1 14 15 28 28 pin vsop (unit: mm) *5.6 0.2 7.6 0.2 0.5 0.2 +0.1 0.675 n material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [ ak53 84 ] ms0225 - e - 00 2003/05 - 21 - marking akm ak5384 v f xxxbyyyyc xxxbyyyyc date code identifier xxxb : lot number (x : digit number, b : alpha character) yyyyc : assembly date (y : digit number, c : alpha character) i m portant notice these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual propert y, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes n o responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applicati ons in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failur e to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliabilit y. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor a grees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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